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1 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 typical application features applications description 14-bit, 125msps/105msps/ 80msps low power dual adcs n communications n cellular base stations n software defined radios n portable medical imaging n multi-channel data acquisition n nondestructive testing n two-channel simultaneously sampling adc n 73.1db snr n 90db sfdr n low power: 189mw/149mw/113mw total 95mw/75mw/57mw per channel n single 1.8v supply n cmos, ddr cmos, or ddr lvds outputs n selectable input ranges: 1v p-p to 2v p-p n 750mhz full power bandwidth s/h n optional data output randomizer n optional clock duty cycle stabilizer n shutdown and nap modes n serial spi port for configuration n 64-pin (9mm 9mm) qfn package the ltc ? 2145-14/ltc2144-14/ltc2143-14 are 2-channel simultaneous sampling 14-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applica- tions with ac performance that includes 73.1db snr and 90db spurious free dynamic range (sfdr). ultralow jitter of 0.08ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 1lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is 1.2lsb rms . the digital outputs can be either full rate cmos, double data rate cmos, or double data rate lvds. a separate output power supply allows the cmos output swing to range from 1.2v to 1.8v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 64k point 2-tone fft, f in = 69mhz, 70mhz, C1dbfs, 125msps cmos, ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd clock control d1_13 d1_0 21454314 ta01a ch 1 analog input output drivers t t t gnd ognd s/h 14-bit adc core ch 2 analog input s/h 14-bit adc core d2_13 d2_0 t t t 125mhz clock frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21454314 ta03b 0 10 20 30 40 50 60
ltc2145-14/ ltc2144-14/ltc2143-14 2 21454314fa absolute maximum ratings supply voltages (v dd , ov dd ) ....................... C0.3v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) .......... C0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) .................................... C0.3v to 3.9v sdo (note 4) ............................................ C0.3v to 3.9v (notes 1, 2) pin configurations digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range ltc2145c, ltc2144c, ltc2143c............. 0c to 70c ltc2145i, ltc2144i, ltc2143i ............ C40c to 85c storage temperature range ................... C65c to 150c full rate cmos output mode double data rate cmos output mode top view up package 64-lead (9mm s 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_3 47 d1_2 46 d1_1 45 d1_0 44 dnc 43 dnc 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_13 37 d2_12 36 d2_11 35 d2_10 34 d2_9 33 d2_8 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of1 59 of2 58 d1_13 57 d1_12 56 d1_11 55 d1_10 54 d1_9 53 d1_8 52 d1_7 51 d1_6 50 d1_5 49 d1_4 v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc 23 dnc 24 d2_0 25 d2_1 26 d2_2 27 d2_3 28 d2_4 29 d2_5 30 d2_6 31 d2_7 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb top view up package 64-lead (9mm s 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_2_3 47 dnc 46 d1_0_1 45 dnc 44 dnc 43 dnc 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_12_13 37 dnc 36 d2_10_11 35 dnc 34 d2_8_9 33 dnc 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of2_1 59 dnc 58 d1_12_13 57 dnc 56 d1_10_11 55 dnc 54 d1_8_9 53 dnc 52 d1_6_7 51 dnc 50 d1_4_5 49 dnc v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc 23 dnc 24 dnc 25 d2_0_1 26 dnc 27 d2_2_3 28 dnc 29 d2_4_5 30 dnc 31 d2_6_7 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb 3 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 order information lead free finish tape and reel part marking* package description temperature range ltc2145cup-14#pbf ltc2145cup-14#trpbf ltc2145up-14 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2145iup-14#pbf ltc2145iup-14#trpbf ltc2145up-14 64-lead (9mm 9mm) plastic qfn C40c to 85c ltc2144cup-14#pbf ltc2144cup-14#trpbf ltc2144up-14 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2144iup-14#pbf ltc2144iup-14#trpbf ltc2144up-14 64-lead (9mm 9mm) plastic qfn C40c to 85c ltc2143cup-14#pbf ltc2143cup-14#trpbf ltc2143up-14 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2143iup-14#pbf ltc2143iup-14#trpbf ltc2143up-14 64-lead (9mm 9mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ double data rate lvds output mode top view up package 64-lead (9mm s 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_2_3 + 47 d1_2_3 C 46 d1_0_1 + 45 d1_0_1 C 44 dnc 43 dnc 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_12_13 + 37 d2_12_13 C 36 d2_10_11 + 35 d2_10_11 C 34 d2_8_9 + 33 d2_8_9 C 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of2_1 + 59 of2_1 C 58 d1_12_13 + 57 d1_12_13 C 56 d1_10_11 + 55 d1_10_11 C 54 d1_8_9 + 53 d1_8_9 C 52 d1_6_7 + 51 d1_6_7 C 50 d1_4_5 + 49 d1_4_5 C v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc 23 dnc 24 d2_0_1 C 25 d2_0_1 + 26 d2_2_3 C 27 d2_2_3 + 28 d2_4_5 C 29 d2_4_5 + 30 d2_6_7 C 31 d2_6_7 + 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb pin configurations ltc2145-14/ ltc2144-14/ltc2143-14 4 21454314fa analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l 0.7 v cm 1.25 v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 125msps per pin, 105msps per pin, 80msps 155 130 100 a a a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1.5 1.5 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 0.08 0.10 ps rms ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 750 mhz converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltc2145-14 ltc2144-14 ltc2143-14 units min typ max min typ max min typ max resolution (no missing codes) l 14 14 14 bits integral linearity error differential analog input (note 6) l C2.6 1 2.6 C2.6 1 2.6 C2.6 1 2.6 lsb differential linearity error differential analog input l C0.9 0.3 0.9 C0.9 0.3 0.9 C0.8 0.3 0.8 lsb offset error (note 7) l C9 1.5 9 C9 1.5 9 C9 1.5 9 mv gain error internal reference external reference l C1.8 1.5 C0.4 0.9 C1.5 1.5 C0.3 1.1 C1.5 1.5 C0.3 1.1 %fs %fs offset drift 10 10 10 v/c full-scale drift internal reference external reference 30 10 30 10 30 10 ppm/c ppm/c gain matching 0.2 0.2 0.2 %fs offset matching 1.5 1.5 1.5 mv transition noise 1.25 1.28 1.20 lsb rms 5 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2145-14 ltc2144-14 ltc2143-14 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 70mhz input 140mhz input l 71.4 73.1 73 72.6 71.2 72.9 72.8 72.4 71.7 73.4 73.3 72.9 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd harmonic 5mhz input 70mhz input 140mhz input l 76 90 89 84 77 90 89 84 78 90 89 84 dbfs dbfs dbfs spurious free dynamic range 3rd harmonic 5mhz input 70mhz input 140mhz input l 79 90 89 84 79 90 89 84 81 90 89 84 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 70mhz input 140mhz input l 86 95 95 95 86 95 95 95 86 95 95 95 dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 140mhz input l 70.8 73 72.8 72.2 70.8 72.8 72.6 72 71.4 73.2 73.1 72.4 dbfs dbfs dbfs crosstalk 10mhz input C110 C110 C110 dbc ltc2145-14/ ltc2144-14/ltc2143-14 6 21454314fa digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance (note 8) 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance (note 8) 3.5 pf digital inputs ( cs , sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs (cmos modes: full data rate and double data rate) ov dd = 1.8v v oh high level output voltage i o = C500a l 1.750 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v ov dd = 1.5v v oh high level output voltage i o = C500a 1.488 v v ol low level output voltage i o = 500a 0.010 v ov dd = 1.2v v oh high level output voltage i o = C500a 1.185 v v ol low level output voltage i o = 500a 0.010 v digital data outputs (lvds mode) v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 247 350 175 454 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 1.125 1.250 1.250 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 7 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions ltc2145-14 ltc2144-14 ltc2143-14 units min typ max min typ max min typ max cmos output modes: full data rate and double data rate v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 v i vdd analog supply current dc input sine wave input l 105.2 105.9 116 82.8 83.3 92 62.8 63.2 70 ma ma i ovdd digital supply current sine wave input, ov dd = 1.2v 8.5 7.1 5.4 ma p diss power dissipation dc input sine wave input, ov dd = 1.2v l 189 201 209 149 159 166 113 120 126 mw mw lvds output mode v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine input, 1.75ma mode sine input, 3.5ma mode l 107.3 108.7 123 84.7 86.1 97 64.6 66.1 75 ma ma i ovdd digital supply current (0v dd = 1.8v) sine input, 1.75ma mode sine input, 3.5ma mode l 35.1 66.3 77 34.8 66 76 34.5 65.7 76 ma ma p diss power dissipation sine input, 1.75ma mode sine input, 3.5ma mode l 256 315 360 215 274 312 178 237 272 mw mw all output modes p sleep sleep mode power 1 1 1 mw p nap nap mode power 16 16 16 mw p diffclk power increase with differential encode mode enabled (no increase for nap or sleep modes) 20 20 20 mw timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltc2145-14 ltc2144-14 ltc2143-14 units min typ max min typ max min typ max f s sampling frequency (note 10) l 1 125 1 105 1 80 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 500 500 4.52 2 4.76 4.76 500 500 5.93 2 6.25 6.25 500 500 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 500 500 4.52 2 4.76 4.76 500 500 5.93 2 6.25 6.25 500 500 ns ns t ap sample-and-hold acquisition delay time 000ns symbol parameter conditions min typ max units digital data outputs (cmos modes: full data rate and double data rate) t d enc to data delay c l = 5pf (note 8) l 1.1 1.7 3.1 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.4 2.6 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency full data rate mode double data rate mode 6 6.5 cycles cycles ltc2145-14/ ltc2144-14/ltc2143-14 8 21454314fa symbol parameter conditions min typ max units digital data outputs (lvds mode) t d enc to data delay c l = 5pf (note 8) l 1.1 1.8 3.2 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.5 2.7 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency 6.5 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5ns t h sck to cs setup time l 5ns t ds sdi setup time l 5ns t dh sdi hold time l 5ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2145), 105mhz (ltc2144), or 80mhz (ltc2143), lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = 1.8v, f sample = 125mhz (ltc2145), 105mhz (ltc2144), or 80mhz (ltc2143), cmos outputs, enc + = single-ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, 5pf load on each digital output unless otherwise noted. the supply current and power dissipation specifications are totals for the entire ic, not per channel. note 10: recommended operating conditions. 9 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 typical performance characteristics ltc2145-14: integral nonlinearity (inl) ltc2145-14: differential nonlinearity (dnl) ltc2145-14: 64k point fft, f in = 5mhz, C1dbfs, 125msps ltc2145-14: 64k point fft, f in = 30mhz, C1dbfs, 125msps ltc2145-14: 64k point fft, f in = 70mhz, C1dbfs, 125msps ltc2145-14: 64k point fft, f in = 140mhz, C1dbfs, 125msps ltc2145-14: 64k point 2-tone fft, f in = 69mhz, 70mhz, C1dbfs, 125msps ltc2145-14: shorted input histogram ltc2145-14: snr vs input frequency, C1dbfs, 125msps, 2v range output code C2.0 C1.0 C0.5 C1.5 inl error (lsb) 0.5 0 1.0 1.5 2.0 21454314 g01 0 4096 8192 12288 16384 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 21454314 g02 0 4096 8192 12288 16384 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21454314 g03 0 10 20 30 40 50 60 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21454314 g04 0 10 20 30 40 50 60 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21454314 g05 0 10 20 30 40 50 60 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21454314 g06 0 10 20 30 40 50 60 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21454314 g07 0 10 20 30 40 50 60 output code 8183 0 count 3000 4000 5000 8185 8187 8189 6000 2000 1000 8191 21454314 g08 input frequency (mhz) 0 72 71 70 74 73 snr (dbfs) 50 100 150 200 250 300 21454314 g09 single-ended encode differential encode ltc2145-14/ ltc2144-14/ltc2143-14 10 21454314fa typical performance characteristics ltc2145-14: sfdr vs input level, f in = 70mhz, 125msps, 2v range ltc2145-14: i vdd vs sample rate, 5mhz, C1dbfs, sine wave input on each channel ltc2145-14: 2nd, 3rd harmonic vs input frequency, C1dbfs, 125msps, 2v range ltc2145-14: io vdd vs sample rate, 5mhz, C1dbfs, sine wave on each input ltc2145-14: snr vs sense, f in = 5mhz, C1dbfs ltc2144-14: integral nonlinearity (inl) ltc2144-14: differential nonlinearity (dnl) ltc2144-14: 64k point fft, f in = 5mhz, C1dbfs, 105msps ltc2145-14: 2nd, 3rd harmonic vs input frequency, C1dbfs, 125msps, 1v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21454314 g10 2nd 3rd 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 218543 g11 2nd 3rd input level (dbfs) 120 90 80 100 110 sfdr (dbc and dbfs) 70 50 60 40 30 21454314 g12 C80 C70 C60 C50 C40 C30 C20 C10 0 dbc dbfs sample rate (msps) 0 75 80 85 110 105 100 95 90 i vdd (ma) 25 50 75 125 100 21454314 g13 cmos outputs lvds outputs sample rate (msps) 0 10 0 20 30 70 60 50 40 io vdd (ma) 25 50 75 125 100 21454314 g14 3.5ma lvds 1.75ma lvds 1.8v cmos sense pin (v) 0.6 71 72 69 70 68 67 66 74 73 snr (dbfs) 0.8 1 0.7 0.9 1.1 1.2 1.3 21454314 g15 output code C2.0 C1.0 C0.5 C1.5 inl error (lsb) 0.5 0 1.0 1.5 2.0 21454314 g16 0 4096 8192 12288 16384 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 21454314 g17 0 4096 8192 12288 16384 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 21454314 g1 11 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 ltc2144-14: 64k point fft, f in = 140mhz, C1dbfs, 105msps typical performance characteristics ltc2144-14: 64k point fft, f in = 30mhz, C1dbfs, 105msps ltc2144-14: 64k point fft, f in = 70mhz, C1dbfs, 105msps ltc2144-14: 64k point 2-tone fft, f in = 69mhz, 70mhz, C1dbfs, 105msps ltc2144-14: shorted input histogram ltc2144-14: snr vs input frequency, C1dbfs, 105msps, 2v range ltc2144-14: 2nd, 3rd harmonic vs input frequency, C1dbfs, 105msps, 2v range ltc2144-14: 2nd, 3rd harmonic vs input frequency, C1dbfs, 105msps, 1v range ltc2144-14: sfdr vs input level, f in = 70mhz, 105msps, 2v range frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 21454314 g19 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 21454314 g20 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 21454314 g21 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 50 21454314 g22 output code 8190 0 count 3000 4000 5000 8192 8194 8196 6000 2000 1000 8198 21454314 g23 input frequency (mhz) 0 72 71 70 74 73 snr (dbfs) 50 100 150 200 250 300 21454314 g24 single-ended encode differential encode 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21454314 g25 2nd 3rd 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 218543 g26 2nd 3rd input level (dbfs) 120 90 80 100 110 sfdr (dbc and dbfs) 70 50 60 40 30 21454314 g27 C80 C70 C60 C50 C40 C30 C20 C10 0 dbc dbfs ltc2145-14/ ltc2144-14/ltc2143-14 12 21454314fa typical performance characteristics ltc2143-14: 64k point fft, f in = 70mhz, C1dbfs, 80msps ltc2143-14: 64k point fft, f in = 140mhz, C1dbfs, 80msps ltc2143-14: 64k point fft, f in = 30mhz, C1dbfs, 80msps ltc2144-14: i vdd vs sample rate, 5mhz, C1dbfs, sine wave input on each channel ltc2144-14: io vdd vs sample rate, 5mhz, C1dbfs, sine wave on each input ltc2144-14: snr vs sense, f in = 5mhz, C1dbfs ltc2143-14: integral nonlinearity (inl) ltc2143-14: differential nonlinearity (dnl) ltc2143-14: 64k point fft, f in = 5mhz, C1dbfs, 80msps sample rate (msps) 0 55 60 65 90 85 80 75 70 i vdd (ma) 25 50 75 100 21454314 g28 cmos outputs lvds outputs sample rate (msps) 0 10 0 20 30 70 60 50 40 io vdd (ma) 25 50 75 100 21454314 g29 3.5ma lvds 1.75ma lvds 1.8v cmos sense pin (v) 0.6 71 72 69 70 68 67 66 74 73 snr (dbfs) 0.8 1 0.7 0.9 1.1 1.2 1.3 21454314 g30 output code inl error (lsb) 21454314 g31 0 4096 8192 12288 16384 C2.0 C1.0 C0.5 C1.5 0.5 0 1.0 1.5 2.0 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 21454314 g32 0 4096 8192 12288 16384 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 21454314 g33 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 21454314 g34 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 21454314 g35 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 21454314 g36 13 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 typical performance characteristics ltc2143-14: shorted input histogram ltc2143-14: 64k point 2-tone fft, f in = 69mhz, 70mhz, C1dbfs, 80msps ltc2143-14: snr vs input frequency, C1dbfs, 80msps, 2v range ltc2143-14: 2nd, 3rd harmonic vs input frequency, C1dbfs, 80msps, 2v range ltc2143-14: 2nd, 3rd harmonic vs input frequency, C1dbfs, 80msps, 1v range ltc2143-14: sfdr vs input level, f in = 70mhz, 80msps, 2v range ltc2143-14: i vdd vs sample rate, 5mhz, C1dbfs, sine wave input on each channel ltc2143-14: io vdd vs sample rate, 5mhz, C1dbfs, sine wave on each input ltc2143-14: snr vs sense, f in = 5mhz, C1dbfs frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 10 20 30 40 21454314 g37 output code 8183 0 count 3000 4000 5000 8185 8187 8189 6000 2000 1000 8191 21454314 g38 input frequency (mhz) 0 72 71 70 74 73 snr (dbfs) 50 100 150 200 250 300 21454314 g39 single-ended encode differential encode 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21454314 g40 2nd 3rd 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 218543 g41 2nd 3rd input level (dbfs) 120 90 80 100 110 sfdr (dbc and dbfs) 70 50 60 40 30 21454314 g42 C80 C70 C60 C50 C40 C30 C20 C10 0 dbc dbfs sample rate (msps) 0 40 45 70 65 60 55 50 i vdd (ma) 20 40 60 80 21454314 g43 cmos outputs lvds outputs sample rate (msps) 0 10 0 20 30 70 60 50 40 io vdd (ma) 20 40 60 80 21454314 g44 3.5ma lvds 1.75ma lvds 1.8v cmos sense pin (v) 0.6 71 72 69 70 68 67 66 74 73 snr (dbfs) 0.8 1 0.7 0.9 1.1 1.2 1.3 21454314 g45 ltc2145-14/ ltc2144-14/ltc2143-14 14 21454314fa pins that are the same for all digital output modes v dd (pins 1, 16, 17, 64): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. v cm1 (pin 2): common mode bias output, nominally equal to v dd /2. v cm1 should be used to bias the common mode of the analog inputs to channel 1. bypass to ground with a 0.1f ceramic capacitor. gnd (pins 3, 6, 14): adc power ground. a in1 + (pin 4): channel 1 positive differential analog input. a in1 C (pin 5): channel 1 negative differential analog input. refh (pins 7, 9): adc high reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. refl (pins 8, 10): adc low reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. par/ ser (pin 11): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or v dd and not be driven by a logic signal. a in2 + (pin 12): channel 2 positive differential analog input. a in2 C (pin 13): channel 2 negative differential analog input. v cm2 (pin 15): common mode bias output, nominally equal to v dd /2. v cm2 should be used to bias the common mode of the analog inputs to channel 2. bypass to ground with a 0.1f ceramic capacitor. enc + (pin 18): encode input. conversion starts on the rising edge. enc C (pin 19): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 20): in serial programming mode, (par/ ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs controls the clock duty cycle stabilizer (see table 2). cs can be driven with 1.8v to 3.3v logic. sck (pin 21): in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck controls the digital output mode (see table 2). sck can be driven with 1.8v to 3.3v logic. sdi (pin 22): in serial programming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi can be used together with sdo to power down the part (see table 2). sdi can be driven with 1.8v to 3.3v logic. ognd (pin 41): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 42): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 61): in serial programming mode, (par/ ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control regis- ters and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo can be used together with sdi to power down the part (see table 2). when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. v ref (pin 62): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the output voltage is nominally 1.25v. pin functions 15 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 pin functions sense (pin 63): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . ground (exposed pad pin 65): the exposed pad must be soldered to the pcb ground. full rate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d2_0 to d2_13 (pins 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): channel 2 digital outputs. d2_13 is the msb. dnc (pins 23, 24, 43, 44): do not connect these pins. clkout C (pin 39): inverted version of clkout + . clkout + (pin 40): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0 to d1_13 (pins 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): channel 1 digital outputs. d1_13 is the msb. of2 (pin 59): channel 2 over/underflow digital output. of2 is high when an overflow or underflow has occurred. of1 (pin 60): channel 1 over/underflow digital output. of1 is high when an overflow or underflow has occurred. double data rate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d2_0_1 to d2_12_13 (pins 26, 28, 30, 32, 34, 36, 38): channel 2 double data rate digital outputs. two data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10, d12) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13) appear when clkout + is high. dnc (pins 23, 24, 25, 27, 29, 31, 33, 35, 37, 43, 44, 45, 47, 49, 51, 53, 55, 57, 59): do not connect these pins. clkout C (pin 39): inverted version of clkout + . clkout + (pin 40): data output clock. the digital outputs normally transition at the same time as the falling and ris- ing edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0_1 to d1_12_13 (pins 46, 48, 50, 52, 54, 56, 58): channel 1 double data rate digital outputs. two data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10, d12) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13) appear when clkout + is high. of2_1 (pin 60): over/underflow digital output. of2_1 is high when an overflow or underflow has occurred. the over/under flow for both channels are multiplexed onto this pin. channel 2 appears when clkout + is low, and channel 1 appears when clkout + is high. double data rate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. d2_0_1 C /d2_0_1 + to d2_12_13 C /d2_12_13 + (pins 25/26, 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): channel 2 double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10, d12) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13) appear when clkout + is high. clkout C /clkout + (pins 39/40): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. ltc2145-14/ ltc2144-14/ltc2143-14 16 21454314fa functional block diagram figure 1. functional block diagram dnc (pins 23, 24, 43, 44): do not connect these pins. d1_0_1 C /d1_0_1 + to d1_12_13 C /d1_12_13 + (pins 45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): channel 1 double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10, d12) ap- pear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13) appear when clkout + is high. of2_1 C /of2_1 + (pins 59/60): over/underflow digital output. of2_1 + is high when an overflow or underflow has occurred. the over/under flow for both channels are multiplexed onto this pin. channel 2 appears when clkout + is low, and channel 1 appears when clkout + is high. diff ref amp ref buf 2.2f 0.1f 0.1f internal clock signals refh refl clock/duty cycle control range select 1.25v reference enc + refh refl enc C correction logic sdo cs ognd of1 ov dd d1_13 clkout C clkout + d1_0 21454314 f01 sense v ref ch 1 analog input 2.2f v cm1 0.1f v dd /2 output drivers mode control registers sck par/ ser sdi t t t gnd s/h 14-bit adc core ch 2 analog input s/h 14-bit adc core v cm2 0.1f of2 d2_13 d2_0 t t t v dd pin functions 17 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 full rate cmos output mode timing all outputs are single-ended and have cmos levels timing diagrams t h t d t c t l b C 6 b C 5 b C 4 b C 3 b C 2 t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input enc C enc + clkout + clkout C d2_0 - d2_13, of2 t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input a C 6 a C 5 a C 4 a C 3 a C 2 d1_0 - d1_13, of1 21454314 td01 ltc2145-14/ ltc2144-14/ltc2143-14 18 21454314fa timing diagrams double data rate cmos output mode timing all outputs are single-ended and have cmos levels t d t t t t d t c t c t l bit 0 a-6 bit 1 a-6 bit 0 a-5 bit 1 a-5 bit 0 a-4 bit 1 a-4 bit 0 a-3 bit 1 a-3 bit 0 a-2 bit 12 a-6 bit 13 a-6 bit 12 a-5 bit 13 a-5 bit 12 a-4 bit 13 a-4 bit 12 a-3 bit 13 a-3 bit 12 a-2 enc C enc + d1_0_1 d1_12_13 t t t bit 0 b-6 bit 1 b-6 bit 0 b-5 bit 1 b-5 bit 0 b-4 bit 1 b-4 bit 0 b-3 bit 1 b-3 bit 0 b-2 bit 12 b-6 bit 13 b-6 bit 12 b-5 bit 13 b-5 bit 12 b-4 bit 13 b-4 bit 12 b-3 bit 13 b-3 bit 12 b-2 of b-6 of a-6 of b-5 of a-5 of b-4 of a-4 of b-3 of a-3 of b-2 d2_0_1 d2_12_13 clkout + clkout C of2_1 21454314 td02 t h t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input 19 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 timing diagrams double data rate lvds output mode timing all outputs are differential and have lvds levels t d t t t t d t c t c t l bit 0 a-6 bit 1 a-6 bit 0 a-5 bit 1 a-5 bit 0 a-4 bit 1 a-4 bit 0 a-3 bit 1 a-3 bit 0 a-2 bit 12 a-6 bit 13 a-6 bit 12 a-5 bit 13 a-5 bit 12 a-4 bit 13 a-4 bit 12 a-3 bit 13 a-3 bit 12 a-2 enc C enc + d1_0_1 + d1_12_13 + t t t bit 0 b-6 bit 1 b-6 bit 0 b-5 bit 1 b-5 bit 0 b-4 bit 1 b-4 bit 0 b-3 bit 1 b-3 bit 0 b-2 bit 12 b-6 bit 13 b-6 bit 12 b-5 bit 13 b-5 bit 12 b-4 bit 13 b-4 bit 12 b-3 bit 13 b-3 bit 12 b-2 of b-6 of a-6 of b-5 of a-5 of b-4 of a-4 of b-3 of a-3 of b-2 d2_0_1 + d2_12_13 + clkout + clkout C of2_1 + d1_0_1 C d1_12_13 C d2_0_1 C d2_12_13 C of2_1 C 21454314 td03 t h t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/ w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 21454314 td04 cs sck sdi r/ w sdo high impedance ltc2145-14/ ltc2144-14/ltc2143-14 20 21454314fa converter operation the ltc2145-14/ltc2144-14/ltc2143-14 are low power, two-channel, 14-bit, 125msps/105msps/80msps a/d converters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially, or single ended for lower power consumption. the digital outputs can be cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system.) many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differen- tially around a common mode voltage set by the v cm1 or v cm2 output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared encode circuit (figure 2). single-ended input for applications less sensitive to harmonic distortion, the a in + input can be driven single-ended with a 1v p-p signal centered around v cm . the a in C input should be connected to v cm and the v cm bypass capacitor should be increased to 2.2f. with a single-ended input, the harmonic distortion and inl will degrade, but the noise and dnl will remain unchanged. input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figure 4 to figure 6) has better balance, resulting in lower a/d distortion. c sample 5pf r on 15 r on 15 v dd v dd ltc2145-14 a in + 21454314 f02 c sample 5pf v dd a in C enc C enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in C 12pf 0.1f v cm ltc2145-14 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 21454314 f03 figure 2. equivalent input circuit. only one of the two analog channels is shown figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz applications information 21 21454314fa ltc2145-14/ ltc2144-14/ltc2143-14 applications information figure 5. recommended front-end circuit for input frequencies from 150mhz to 250mhz figure 6. recommended front-end circuit for input frequencies above 250mhz amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac-coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figure 4 to figure 6) should convert the signal to differential before driving the a/d. figure 4. recommended front-end circuit for input frequencies from 5mhz to 150mhz reference the ltc2145-14/ltc2144-14/ltc2143-14 has an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the v ref , refh and refl pins should be bypassed as shown in figure 8. a low inductance 2.2f interdigitated capacitor is recommended for the bypass between refh and refl. this type of capacitor is available at a low cost from multiple suppliers. 25 12 12 25 50 0.1f a in + a in C 8.2pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 21454314 f04 ltc2145-14 25 25 50 0.1f a in + a in C 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 21454314 f05 ltc2145-14 25 25 50 0.1f 4.7nh 4.7nh a in + a in C 0.1f v cm analog input t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 21454314 f06 ltc2145-14 t1 0.1f 0.1f 25 25 200 200 0.1f a in + a in C 0.1f 12pf 12pf v cm ltc2145-14 21454314 f07 C C + + analog input high speed differential amplifier 0.1f figure 7. front-end circuit using a high speed differential amplifier ltc2145-14/ ltc2144-14/ltc2143-14 22 21454314fa applications information v ref refh refh sense c1 tie to v dd for 2v range; tie to gnd for 1v range; 3 " / ( & |